It is desirable to provide certain types of application-specific integrated circuits (ASICs) with significant memory capability, including some combination of large amounts of memory, high operating speed, and high bandwidth. Providing such capability can be problematic. Memory occupies space and consumes power. In an ASIC, it is desirable to conserve space and power resources. A variety of factors place practical limits upon clock speed. Therefore, other avenues for enhancing memory performance may be preferable to simply increasing clock speed. One potential way to increase the amount of memory that is effectively available to an ASIC without actually adding memory to the ASIC design or increasing clock speed is to provide external, i.e., off-chip, memory. However, to provide a significant increase in memory bandwidth, such off-chip solutions generally must consume substantial amounts of power and tie up a substantial number of ASIC input/output (I/O) pins. It would be desirable to effectively increase memory bandwidth without unduly increasing memory quantity or clock speed in the ASIC or resorting to off-chip solutions.
It is known that some aspects of memory performance can be enhanced by dividing physical memory into logical data storage units known as memory banks. Memory banking schemes can be employed in a parallel processing system to allow two or more processes to simultaneously access the data storage. For example, in a memory banked system, a first process may be able to read a memory location in a first memory bank at the same time that a second process is able to write to a memory location in a second memory bank. Dividing the memory into banks reduces the likelihood that two processes will attempt to simultaneously access the same bank, thereby effectively increasing bandwidth. However, for memory banking to work properly, the system must provide some means for solving potential bank conflicts where a first process attempts to simultaneously access the same bank as the second process. One known solution to this potential problem is for the system to space the two memory accesses so that they occur sequentially rather than simultaneously.
Dual-port memory is a type of memory device that allows simultaneous read and write access by two processes during a single clock cycle. That is, during a single clock cycle, a first process can write to or read from the memory while a second process can, independently of the first process, write to or read from the same memory device. However, dual-port memory is relatively uneconomical compared with single-port memory and occupies significantly more space on an ASIC or other integrated circuit chip than single-port memory. It is also known to enhance a single-port memory system by increasing (e.g., doubling) the clock speed to allow a read operation and a write operation to occur sequentially but within a single clock cycle of one another, thereby providing an effect that approaches the simultaneity of true dual-port memory.